A conventional flash EEPROM memory cell typically includes spaced source and drain regions diffused into a semiconductor substrate and a channel region provided therebetween. In addition, the conventional flash memory cell includes an electrically isolated floating gate provided over the channel region, and a control gate disposed above the floating gate. By applying appropriate voltages to the source, drain and control gate, charge is either stored on or removed from the floating gate, and thus data, in the form of such charge, is stored in, or erased from, the memory cell. The presence or absence of charge on the floating gate determines whether current flows between the source and drain regions when the memory cell is selected. Such current can be sensed by appropriate circuitry as a binary “1” stored in the memory cell. Alternatively, if no current is sensed, a binary “0” is considered to be stored in the memory cell. It is also known to arbitrarily associate sensed current and no sensed current with binary “0” and “1”, respectively. Multiple EEPROM memory cells are typically combined to form memory arrays.
Typically, EEPROM memory cells are arranged in an array of rows and columns. Bit lines in the array connect the drains of the memory cells in any given column, and word lines connect the gates of the memory cells in any given row. The sources of each memory cell are often connected to ground.
In order to program a particular memory cell, a bit line corresponding to the column in which the selected memory cell is located is typically driven to a relatively high voltage. In addition, a word line associated with the row in which the selected memory cell is located is also driven to a high voltage. Thus, the drain and gate of the selected memory cell, which is located at the intersection of these bit and word lines, are set to high voltages to create a current that supplies charge to the floating gate.
During programming, however, the drains of non-selected memory cells in the column in which the selected memory cell is located also receive the potential of the relatively high voltage bit line. As a result, an off-state or leakage current may flow between the sources and drains of those nonselected memory cells. Although the leakage current associated with a single memory cell may be minimal, collectively, the leakage currents through each nonselected cell can approximate or even exceed the current flowing in the selected memory cell. Accordingly, a charge pump circuit that supplies the bit line programming voltage may not be able to maintain that voltage at a sufficiently high level to insure adequate memory cell programming.
A larger charge pump circuit may be provided in order to generate a higher bit line programming voltage. The larger charge pump circuit, however, would occupy more chip area, thereby limiting the number of memory cells that can be provided on a semiconductor chip.
The present invention is directed to overcome one or more of the problems of the prior art.